This invention relates to a semiconductor device, and more particularly to a semiconductor device having at a major surface of a semiconductor body alternate regions of opposite conductivity type, a first set of electrode fingers at a first metallization level on said major surface and contacting the regions of a first conductivity type, and a second set of electrode fingers at the first metallization level on said major surface and contacting the regions of the second opposite conductivity type. The invention also relates to a method of manufacturing such a semiconductor device.
A semiconductor device having the features mentioned above is described hereinafter as having an interdigitated electrode configuration. High voltage power semiconductor devices such as a gate turn-off thyristor (hereinafter referred to as a "GTO") and a high voltage bipolar transistor may adopt such an interdigitated electrode configuration in order to optimize high frequency switching performance.
A so-called gate controlled switch (which is synonymous with a GTO) having the features mentioned above is known from the paper by Hayashi et al. entitled "A High-Power Gate-Controlled Switch Using New Life Time Control Method" which appeared in IEEE Transactions on Electron Devices, Vol. ED-28, No. 3, Mar. 1981, at pages 246-251 (see particularly FIG. 4). This shows a semiconductor device comprising a semiconductor body having at a major surface alternate regions of opposite conductivity types. A first set of electrode fingers contacts the regions of a first conductivity type and a second set of electrode fingers contacts the regions of the second opposite conductivity type. The first and second sets of electrodes are thus arranged in an interdigitated configuration at the same metallization level. A first electrically conductive bonding pad is electrically connected to the electrodes of the first set, and a second electrically conductive bonding pad which is at the same metallization level as the first bonding pad and which is electrically isolated from the first bonding pad is electrically connected to the electrodes of the second set.
For both GTOs and high voltage bipolar power transistors the interdigitated electrode configuration comprises two sets of electrode fingers. One set of electrode fingers constitutes a main current-carrying electrode and the other set of electrode fingers constitutes a control electrode. The main current-carrying electrode, which is the cathode in the case of a GTO and the emitter electrode in the case of a power transistor, may carry high currents of 1 amp and upwards. The control electrode, which is the gate electrode for a GTO and the base electrode for a power transistor, may carry a current ranging from hundreds of milliamps to several amps.
As shown in the above-mentioned paper by Hayashi et al the cathode electrode fingers are electrically connected to a bonding pad at the center of the device and the gate electrode fingers are electrically connected to two bonding pads at diametrically opposed corners of the device. All the bonding pads are relatively large in area so that large diameter wires can be bonded thereto for high current handling capability. The bonding pads are formed on an insulating layer at the same major surface of the semiconductor body as the two sets of electrodes. Moreover, the bonding pads are at the same metallization level as the electrode fingers. The metallization thus has a comb-like configuration. However, because none of the bonding pads forms part of the interdigitated configuration, they do not usefully contribute to the device's switching properties and from this viewpoint they waste useful area of the semiconductor surface. In general the total bonding pad area is not insignificant and may be more than one third of the overall useful device area.
Furthermore with such a device it is necessary to provide over the top of the interdigitated electrode configuration a protective layer to guard against damage of the fine electrode structure.
Also, with this prior art device the various electrode fingers have different lengths which may, during operation, give rise to different voltage drops along different electrode fingers causing uneven current density distribution and a non-uniform turn-off characteristic. In fact, current localization may even limit turn-off performance of the device.
A semiconductor device is known which, compared with the device described above, achieves a saving in useful area occupied by the bonding pads. In this case the device has a mesa configuration. One set of electrode fingers is provided on the mesa plateaux and the second set of electrode fingers in the troughs. Thus one set of electrode fingers is at a higher level than the other set so that a plate-like bonding pad can be provided in contact with the electrode fingers at the upper level, but electrically isolated from the electrode fingers at the lower level. The lower-level electrode fingers are integral with and so electrically connected to a bonding pad which is present on an insulating layer at the surface of the semiconductor body. Thus although this device goes some way to solving the problem of wasting useful device area it still occupies useful area for the bonding pad (or pads) for one of the sets of electrode fingers.
British Patent GB No. 1322141 discloses a transistor (see FIG. 4) in which the base and emitter are present as alternate regions of opposite conductivity type at the major surface of a semiconductor body. The base is contacted by electrode fingers formed by a platinum silicide grid surrounding each emitter region. An insulating layer is disposed over the grid and has emitter contact windows exposing each emitter region at the surface. An emitter contact layer forming a bonding pad is disposed over the insulating layer and extends into the windows, directly contacting the emitter regions. The emitter bonding pad is thus provided at a second metallization level over the active area of the transistor, which again goes some way to saving useful device area. However, the bonding pads for the base are disposed on an insulating layer at the surface of the semiconductor body outside the active area of the transistor, and therefore still occupy useful device area. It is noted also that this device has only one set of electrode fingers, viz. the base grid, which are formed at a first metallization level because the emitter regions are contacted directly by the emitter bonding pad at the second metallization level. In both its structure and manufacture, this transistor differs markedly from the GTO disclosed by Hayashi et al, which in these respects is more akin to the device of the present invention.
In European Patent application No. 0,051,459 there is disclosed a G.T.O device in which the two sets of interdigitated electrode fingers are contacted by two thin comb-like copper foils in an interdigitated manner. The foils themselves can be used instead of wire bonds for the electrical connections, thus dispensing altogether with the need for bonding pads. However this solution is not wholly satisfactory because it introduces new problems. For example, the copper foil has to be made separately and then positioned and fixed to the semiconductor device. Not only is the foil delicate and so prone to damage but the dimensions can be so small that alignment with the fine electrode fingers is very difficult and consequently undesirable short-circuits may result. To overcome the problem of delicacy the foil may be provided with a backing film for reinforcement but this inevitably adds to the expense and complexity of manufacture. The expense is already relatively high because of the soft soldering process employed and the materials used therefor. Moreover the choice of material for the backing film is limited because it must be transparent to enable visual alignment of the foil and the electrode fingers below.